1. Field of the Invention
The present invention relates to a thin-film transistor used for an active matrix type liquid crystal display device and a method of manufacturing the same.
2. Description of the Related Art
An active matrix type liquid crystal display device (to be referred to as an LCD hereinafter) has a TFT array. This TFT array is constituted by a large number of thin-film transistors (to be referred to as TFTs hereinafter) and display electrodes arranged in a matrix form. The TFT array comprises an insulating transparent substrate, a plurality of address wiring layers formed on the substrate to extend in the row direction, and a plurality of data wiring layers formed on the substrate in the column direction. The address and data wiring layers cross each other at right angles. The TFTs are respectively arranged at the intersections between the address wiring layers and the data wiring layers.
The gate electrodes of the TFTs of each row are connected to the corresponding address wiring layers, respectively. The drain electrodes of the TFTs of each column are connected to the corresponding data wiring layers, respectively. The display electrodes are respectively arranged in the regions defined by the address and data wiring layers and are connected to the source electrodes of the corresponding TFTs.
As a TFT used for such a conventional LCD, for example, a TFT having an arrangement like the one shown in FIGS. 1 and 2 is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 3-9569. FIG. 1 is a sectional view of a TFT. FIG. 2 is a plan view of a TFT pattern. FIG. 1 is a sectional view taken along a line I--I of the pattern shown in FIG. 2.
The TFT shown in FIGS. 1 and 2 is formed in the following manner. First, a metal layer consisting of Al (aluminum), an Al alloy, Ta (tantalum), a Ta alloy, Cr (chromium), or the like is formed on an insulating transparent substrate 1 such as a glass substrate by sputtering. The formed metal layer is then patterned by photoetching or the like to form a gate electrode 2. The surface of the gate electrode 2 is anodized to form a first gate insulating film 3.
An SiN (silicon nitride) film 4 serving as the second gate insulating film, an n.sup.- -type amorphous silicon layer 5 serving as a semiconductor layer, and an n.sup.+ -type amorphous silicon layer 6 doped with an impurity are sequentially deposited on the substrate and the first gate insulating film. The n.sup.- -type amorphous silicon layer 5 and the n.sup.+ -type amorphous silicon layer 6 are patterned to perform element isolation.
Subsequently, a transparent film consisting of ITO (indium tin oxide) is formed on the resultant structure by sputtering. The ITO film is patterned to form a transparent display electrode 7.
An Mo (molybdenum) film 8 and an Al film 9 are deposited on the resultant structure by sputtering in the order named. These films are then patterned to form a source electrode 11, a drain electrode 12, and a data wiring layer 13. The source electrode 11 is constituted by an Mo film portion 8a and an Al film portion 9a formed thereon. The drain electrode 12 is constituted by an Mo film portion 8b and an Al film portion 9b formed thereon. The data wiring layer 13 is constituted by an Mo film portion 8c and an Al film portion 9c formed thereon.
A partial region of the Mo film portion 8a of the source electrode 11 overlaps an end portion of the display electrode 7 and is electrically connected thereto. Etching for patterning the Al film 9 and the Mo film 8 is performed by using a phosphoric-acid-based etching solution (a mixture of phosphoric acid, nitric acid, acetic acid, and water). The Mo film portions 8a and 8b serve as ohmic barrier layers for the n.sup.+ -type amorphous silicon layer 6 and the Al film portions 9a and 9b. Therefore, ohmic contacts can be obtained between the n.sup.+ -type amorphous silicon layer 6 and the Al film portion 9a, and between the n.sup.+ -type amorphous silicon layer 6 and the Al film portion 9b. Since Al has a low resistance, the Al film portions 9a, 9b, and 9c serve as main electrodes or main wires.
Subsequently, dry etching is performed by using the source electrode 11 and the drain electrode 12 as masks to remove a portion of the n.sup.+ -type amorphous silicon layer 6 between these electrodes, thereby forming a channel region of a TFT.
A surface protective film 10 consisting of SiN is formed on the resultant structure by the plasma CVD method. By removing a portion, of the surface protective film 10, formed on the display electrode 7, a TFT for a liquid crystal display device is completed.
As shown in FIG. 2, an address wiring layer 2i is formed to extend in the row direction, and a region serving as the gate electrode 2 protrudes into a prospective TFT formation region. The data wiring layer 13 extends in the column direction to cross the address wiring layer 2i at a right angle. The region 12 of the data wiring layer 13 protrudes into the prospective TFT formation region. The region 12 serves as a drain electrode.
The above-described TFT for an LCD is advantageous in that the Mo film and the Al film for forming the source electrode 11 and the drain electrode 12 can be etched by using the same etching solution. In contrast to this advantage, the following drawbacks are posed.
The etching rate of the Mo film 8 serving as an ohmic barrier layer is four to six times that of the Al film 9. For this reason, the Al film 9 is etched more than the Mo film 8. Consequently, after etching, the Al film 9 tends to have an overhanging cross-sectional shape, which tends to cause peeling or stripping of the Al film 9. If peeling or stripping of the Al film 9 occurs, disconnection of the source electrode 11 and the drain electrode 12 tends to occur in the subsequent process. In addition, a peeled Al film portion adheres to another wire. As a result, a short circuit tends to occur. For this reason, line or point defects of a liquid crystal display element tend to occur.
In order to prevent the above-mentioned overhanging, the Mo film 8 may not be formed so as to directly form the Al film 9 on the n.sup.+ -type amorphous silicon layer 6 and the ITO film (display electrode) 7. In this arrangement, however, no ohmic contact can be obtained between the n.sup.+ -type amorphous silicon layer 6 and the Al film 9. When a resist film is formed on the Al film 9 to be developed for the patterning of the Al film 9, an alkaline developing solution flows through pin holes of the Al film 9 to permeate between the ITO film 7 and the Al film 9. For this reason, a battery reaction occurs between the Al film 9 and the ITO film 7 to cause peeling of the Al film 9 and the ITO film 7, thus posing a new problem.
In addition, in order to prevent the above-mentioned overhanging, an Mo--W (tungsten) alloy film may be formed under the Al film 9 to control the etching rate. If, however, an Mo--W alloy film is formed, since the quality (composition ratio and the like) and repeatability of a film formed by sputtering are poor, it is difficult to control the etching rate. Furthermore, since an alloy target needs to be formed for a sputtering process, the manufacturing cost increases.
In the TFT having the arrangement shown in FIGS. 1 and 2, the Mo film portion 8a is formed to overlap the display electrode 7 so as to electrically connect the display electrode 7 to the source electrode 11. In this case, as the area of the overlapping portion increases, the substantial area of the display electrode 7 decreases. For this reason, only a small contact area is allowed between the display electrode 7 and the Mo film portion 8a, and hence it is difficult to ensure satisfactory electrical connection.